1. Field of the Invention
The present invention relates to, e.g., a semiconductor memory device capable of storing data consisting of two or more bits in a single memory cell.
2. Description of the Related Art
There has been proposed a non-volatile semiconductor memory device which is a NAND flash memory using an EEPROM and can store multivalued data in a single memory cell (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-195280). In a NAND flash memory, all or a half of memory cells arranged in a row direction are connected with corresponding latch circuits through bit lines, respectively. Each latch circuit holds data in data write and read operations. Data is collectively written into or read from all or a half of cells arranged in the row direction.
Meanwhile, miniaturization of an element has advanced, and a distance between cells is becoming short. In addition to this, a capacity between floating gates (an FG-FG capacity) of cells adjacent to each other is increasing. Therefore, there occurs a problem that a threshold voltage of a cell in which data has been previously written fluctuates when data is written in an adjacent cell. In particular, since a multivalued memory which stores multi-bit data in one cell stores corresponding data based on a plurality of threshold voltages, it is required to control a distribution of one threshold voltage to be extremely narrowed. Therefore, a problem of a fluctuation in a threshold voltage due to writing data in an adjacent cell is prominent.
In order to solve this problem, the following method has been considered. For example, when i-bit (i<k) data is stored in a memory cell capable of storing k-bit data, data consisting of i or smaller bits is written in an adjoining cell before storing the next data. As a result, it is possible to ideally suppress a fluctuation in a threshold voltage to 1/3 in the case of a cell storing four values, 1/7 in the case of a cell storing eight values, and 1/(n−1) in the case of a cell storing n values (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
The above-described method suppresses a fluctuation in a threshold voltage with respect to a cell having data written therein, but this method is not applied to a cell having no data written therein after erasing data. Therefore, a threshold voltage of a cell in an erased state (which will be referred to as an erase cell hereinafter) is affected by data which is written in an adjacent cell. Therefore, a threshold voltage of an erase cell must be set low in accordance with this influence. However, when a threshold voltage of an erase cell is set lower, a variation of a threshold voltage is increased when writing necessary data, and suppressing the threshold voltage to an ideal value is difficult. Therefore, the present invention provides a semiconductor memory device capable of suppressing a change in a threshold voltage of an erase cell.